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NXP Semiconductors /MIMXRT1052 /LCDIF /CTRL2_CLR

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Interpret as CTRL2_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RGB)EVEN_LINE_PATTERN 0 (RGB)ODD_LINE_PATTERN 0 (BURST_LEN_8)BURST_LEN_8 0 (REQ_1)OUTSTANDING_REQS

ODD_LINE_PATTERN=RGB, OUTSTANDING_REQS=REQ_1, EVEN_LINE_PATTERN=RGB

Description

LCDIF General Control2 Register

Fields

EVEN_LINE_PATTERN

This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

0 (RGB): RGB

1 (RBG): RBG

2 (GBR): GBR

3 (GRB): GRB

4 (BRG): BRG

5 (BGR): BGR
ODD_LINE_PATTERN

This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

0 (RGB): RGB

1 (RBG): RBG

2 (GBR): GBR

3 (GRB): GRB

4 (BRG): BRG

5 (BGR): BGR
BURST_LEN_8

By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)
OUTSTANDING_REQS

This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

0 (REQ_1): REQ_1

1 (REQ_2): REQ_2

2 (REQ_4): REQ_4

3 (REQ_8): REQ_8

4 (REQ_16): REQ_16

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data